Auto Page CPX-3600 Especificações

August 2010 Doc ID 13829 Rev 1 1/2431ST72321xx-Auto8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,ADC, 5 timers, SPI, SCI, I2C interfaceFeaturesM

Contents ST72321xx-Auto10/243 Doc ID 13829 Rev 119.9.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-bit timer ST72321xx-Auto100/243 Doc ID 13829 Rev 1Figure 41. Timer block diagram1. If IC, OC and TO interrupt request have separate vectors, then t

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 101/24316-bit read sequenceThe 16-bit read sequence (from either the Counter Register or the Alternate C

16-bit timer ST72321xx-Auto102/243 Doc ID 13829 Rev 113.3.2 External clockThe external clock (where available) is selected if CC0 = 1 and CC1 = 1 in t

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 103/24313.3.3 Input captureIn this section, the index, i, may be 1 or 2 because there are two input capt

16-bit timer ST72321xx-Auto104/243 Doc ID 13829 Rev 15 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any trans

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 105/24313.3.4 Output compareIn this section, the index, i, may be 1 or 2 because there are two output co

16-bit timer ST72321xx-Auto106/243 Doc ID 13829 Rev 1If the timer clock is an external clock, the formula is:Where:t = Output compare period (in sec

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 107/243Figure 48. Output compare block diagram Figure 49. Output compare timing diagram, fTIMER =fCPU/2F

16-bit timer ST72321xx-Auto108/243 Doc ID 13829 Rev 113.3.6 One Pulse modeOne Pulse mode enables the generation of a pulse when an external event occu

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 109/243The OC1R register value required for a specific timing application can be calculated using the fo

ST72321xx-Auto ContentsDoc ID 13829 Rev 1 11/24322.1.7 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-bit timer ST72321xx-Auto110/243 Doc ID 13829 Rev 1Figure 53. Pulse width modulation mode timing example with 2 output compare functionsNote: On tim

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 111/243Figure 54. Pulse width modulation cycle flowchartIf OLVL1 = 1 and OLVL2 = 0 the length of the pos

16-bit timer ST72321xx-Auto112/243 Doc ID 13829 Rev 113.4 Low power modes 13.5 Interrupts Note: The 16-bit timer interrupt events are

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 113/24313.7 16-bit timer registersEach timer is associated with 3 control and status registers, and wit

16-bit timer ST72321xx-Auto114/243 Doc ID 13829 Rev 113.7.2 Control register 2 (CR2) 3FOLV1Forced Output Compare 1This bit is set an

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 115/243 13.7.3 Control/status register (CSR) 5OPMOne Pulse Mode0: One Pulse Mode is not

16-bit timer ST72321xx-Auto116/243 Doc ID 13829 Rev 1 13.7.4 Input capture 1 high register (IC1HR)This is an 8-bit read only register that co

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 117/24313.7.5 Input capture 1 low register (IC1LR)This is an 8-bit read only register that contains the

16-bit timer ST72321xx-Auto118/243 Doc ID 13829 Rev 113.7.9 Output compare 2 low register (OC2LR)This is an 8-bit register that contains the low part

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 119/24313.7.13 Alternate counter low register (ACLR)This is an 8-bit register that contains the low part

List of tables ST72321xx-Auto12/243 Doc ID 13829 Rev 1List of tablesTable 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16-bit timer ST72321xx-Auto120/243 Doc ID 13829 Rev 1 Related documentationSCI software communications using 16-bit timer (AN 973)Real-time Cl

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 121/24314 Serial peripheral interface (SPI)14.1 Introduction The Serial Peripheral

Serial peripheral interface (SPI) ST72321xx-Auto122/243 Doc ID 13829 Rev 1Figure 55. Serial peripheral interface block diagram14.3.1 Functional descri

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 123/243Figure 56. Single master/single slave application14.3.2 Slave select manage

Serial peripheral interface (SPI) ST72321xx-Auto124/243 Doc ID 13829 Rev 1Figure 57. Generic SS timing diagramFigure 58. Hardware/Software slave selec

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 125/24314.3.4 Master mode transmit sequenceWhen software writes to the SPIDR regis

Serial peripheral interface (SPI) ST72321xx-Auto126/243 Doc ID 13829 Rev 1The SPIF bit can be cleared during a second transmission; however, it must b

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 127/243Figure 59. Data clock timing diagramMSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1

Serial peripheral interface (SPI) ST72321xx-Auto128/243 Doc ID 13829 Rev 114.5 Error flags14.5.1 Master mode fault (MODF)Master mode fault occurs whe

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 129/243Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence14.

ST72321xx-Auto List of tablesDoc ID 13829 Rev 1 13/243Table 49. PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial peripheral interface (SPI) ST72321xx-Auto130/243 Doc ID 13829 Rev 114.6 Low power modes 14.6.1 Using the SPI to wake up the MCU from

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 131/24314.8 SPI registers14.8.1 Control register (SPICR) SPICR Re

Serial peripheral interface (SPI) ST72321xx-Auto132/243 Doc ID 13829 Rev 1 14.8.2 Control/status register (SPICSR) 1:0 SPR[1:

ST72321xx-Auto Serial peripheral interface (SPI)Doc ID 13829 Rev 1 133/24314.8.3 Data I/O register (SPIDR) The SPIDR register is used to tran

Serial peripheral interface (SPI) ST72321xx-Auto134/243 Doc ID 13829 Rev 1Warning: A write to the SPIDR register places data directly into the shift r

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 135/24315 Serial communications interface (SCI)15.1 IntroductionThe Serial Comm

Serial communications interface (SCI) ST72321xx-Auto136/243 Doc ID 13829 Rev 115.3 General descriptionThe interface is externally connected to another

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 137/243Figure 62. SCI block diagramWAKEUPUNITRECEIVERCONTROLSRTRANSMITCONTROLTD

Serial communications interface (SCI) ST72321xx-Auto138/243 Doc ID 13829 Rev 115.4 Functional descriptionThe block diagram of the Serial Control Inter

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 139/24315.4.2 TransmitterThe transmitter can send data words of either 8 or 9 b

List of tables ST72321xx-Auto14/243 Doc ID 13829 Rev 1Table 101. Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . .

Serial communications interface (SCI) ST72321xx-Auto140/243 Doc ID 13829 Rev 1bit by software the SCI insert a logic 1 bit at the end of the last brea

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 141/243When an overrun error occurs: ● The OR bit is set.● The RDR content is n

Serial communications interface (SCI) ST72321xx-Auto142/243 Doc ID 13829 Rev 1Figure 64. SCI baud rate and extended prescaler block diagramFraming err

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 143/243Conventional baud rate generationThe baud rate for the receiver and tran

Serial communications interface (SCI) ST72321xx-Auto144/243 Doc ID 13829 Rev 1A receiver wakes up by Idle Line detection when the Receive line has rec

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 145/243Consequently, the bit length must be long enough so that the 8th, 9th an

Serial communications interface (SCI) ST72321xx-Auto146/243 Doc ID 13829 Rev 1Figure 65. Bit sampling in reception mode15.5 Low power modes 1

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 147/24315.7 SCI registers15.7.1 Status register (SCISR) Idle Line Detec

Serial communications interface (SCI) ST72321xx-Auto148/243 Doc ID 13829 Rev 14IDLEIdle line detectThis bit is set by hardware when an Idle Line is de

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 149/24315.7.2 Control register 1 (SCICR1) SCICR1 Reset value:

ST72321xx-Auto List of figuresDoc ID 13829 Rev 1 15/243List of figuresFigure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . .

Serial communications interface (SCI) ST72321xx-Auto150/243 Doc ID 13829 Rev 115.7.3 Control register 2 (SCICR2) 0PIEParity interrup

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 151/24315.7.4 Data register (SCIDR)This register contains the Received or Trans

Serial communications interface (SCI) ST72321xx-Auto152/243 Doc ID 13829 Rev 1 15.7.6 Extended receive prescaler division register (SCIERPR)Th

ST72321xx-Auto Serial communications interface (SCI)Doc ID 13829 Rev 1 153/243 15.7.7 Extended transmit prescaler division register (SCIETPR)T

Serial communications interface (SCI) ST72321xx-Auto154/243 Doc ID 13829 Rev 1 Table 80. SCI register map and reset valuesAddress (Hex.)Regist

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 155/24316 I2C bus interface (I2C)16.1 IntroductionThe I2C bus interface serves as an interfac

I2C bus interface (I2C) ST72321xx-Auto156/243 Doc ID 13829 Rev 116.3 General descriptionIn addition to receiving and transmitting data, this interface

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 157/24316.3.3 SDA/SCL line controlTransmitter modeThe interface holds the clock line low bef

I2C bus interface (I2C) ST72321xx-Auto158/243 Doc ID 13829 Rev 116.4 Functional descriptionRefer to the CR, SR1 and SR2 registers in Section 16.7 for

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 159/243Closing slave communicationAfter the last data byte is transferred, a Stop Condition i

List of figures ST72321xx-Auto16/243 Doc ID 13829 Rev 1Figure 49. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . .

I2C bus interface (I2C) ST72321xx-Auto160/243 Doc ID 13829 Rev 1Slave address transmissionThen the slave address is sent to the SDA line via the inter

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 161/243Error cases● BERR: Detection of a Stop or a Start condition during a byte transfer. In

I2C bus interface (I2C) ST72321xx-Auto162/243 Doc ID 13829 Rev 1Figure 68. Transfer sequencing7-bit Slave receiver:7-bit Slave transmitter:7-bit Maste

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 163/24316.5 Low power modes 16.6 InterruptsFigure 69. Interrupt control logic diagra

I2C bus interface (I2C) ST72321xx-Auto164/243 Doc ID 13829 Rev 116.7 Register description16.7.1 I2C control register (CR) CR Reset va

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 165/24316.7.2 I2C status register 1 (SR1) 1STOPGeneration of a Stop conditionThis bit

I2C bus interface (I2C) ST72321xx-Auto166/243 Doc ID 13829 Rev 16 ADD1010-bit addressing in Master modeThis bit is set by hardware when the master has

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 167/24316.7.3 I2C status register 2 (SR2) 1M/SLMaster/SlaveThis bit is set b

I2C bus interface (I2C) ST72321xx-Auto168/243 Doc ID 13829 Rev 116.7.4 I2C clock control register (CCR) 2ARLOArbitration lostThis bit

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 169/24316.7.5 I2C data register (DR) 16.7.6 I2C own address register (OAR1)

ST72321xx-Auto List of figuresDoc ID 13829 Rev 1 17/243Figure 101. ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C bus interface (I2C) ST72321xx-Auto170/243 Doc ID 13829 Rev 1 16.7.7 I2C own address register (OAR2) Table 88. OAR1 regist

ST72321xx-Auto I2C bus interface (I2C)Doc ID 13829 Rev 1 171/243 Table 90. I2C register map and reset valuesAddress (Hex.)Register label76543

10-bit A/D converter (ADC) ST72321xx-Auto172/243 Doc ID 13829 Rev 117 10-bit A/D converter (ADC)17.1 IntroductionThe on-chip Analog to Digital Conver

ST72321xx-Auto 10-bit A/D converter (ADC)Doc ID 13829 Rev 1 173/24317.3 Functional descriptionThe conversion is monotonic, meaning that the result nev

10-bit A/D converter (ADC) ST72321xx-Auto174/243 Doc ID 13829 Rev 117.3.3 Changing the conversion channelThe application can change channels during c

ST72321xx-Auto 10-bit A/D converter (ADC)Doc ID 13829 Rev 1 175/24317.6.2 Data register (ADCDRH) 5ADON A/D Converter onThis bit is se

10-bit A/D converter (ADC) ST72321xx-Auto176/243 Doc ID 13829 Rev 117.6.3 Data register (ADCDRL) 17.6.4 ADC register map and reset va

ST72321xx-Auto Instruction setDoc ID 13829 Rev 1 177/24318 Instruction set18.1 CPU addressing modesThe CPU features 17 different addressing modes whi

Instruction set ST72321xx-Auto178/243 Doc ID 13829 Rev 118.1.1 InherentAll Inherent instructions consist of a single byte. The opcode fully specifies

ST72321xx-Auto Instruction setDoc ID 13829 Rev 1 179/24318.1.2 ImmediateImmediate instructions have 2 bytes. The first byte contains the opcode and th

Description ST72321xx-Auto18/243 Doc ID 13829 Rev 11 DescriptionThe ST72321xx-Auto Flash and ROM devices are members of the ST7 microcontroller family

Instruction set ST72321xx-Auto180/243 Doc ID 13829 Rev 118.1.5 Indirect (short, long)The required data byte to do the operation is found by its memory

ST72321xx-Auto Instruction setDoc ID 13829 Rev 1 181/24318.1.7 Relative (direct, indirect)This addressing mode is used to modify the PC register valu

Instruction set ST72321xx-Auto182/243 Doc ID 13829 Rev 118.2.1 Using a prebyteThe instructions are described with one to four opcodes.In order to exte

ST72321xx-Auto Instruction setDoc ID 13829 Rev 1 183/243 Table 103. Instruction set overviewMnemo Description Function/Example Dst Src I1 H I0

Instruction set ST72321xx-Auto184/243 Doc ID 13829 Rev 1JRUGT Jump if (C + Z = 0) Unsigned >JRULE Jump if (C + Z = 1) Unsigned <=LD Load dst <

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 185/24319 Electrical characteristics19.1 Parameter conditionsUnless otherwise specified, a

Electrical characteristics ST72321xx-Auto186/243 Doc ID 13829 Rev 119.2 Absolute maximum ratingsStresses above those listed as “absolute maximum rati

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 187/24319.2.2 Current characteristics 19.2.3 Thermal characteristics Tab

Electrical characteristics ST72321xx-Auto188/243 Doc ID 13829 Rev 119.3 Operating conditions19.3.1 General operating conditions Note: Some te

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 189/24319.3.2 Operating conditions with low voltage detector (LVD) Subject to general oper

ST72321xx-Auto DescriptionDoc ID 13829 Rev 1 19/243Figure 1. Device block diagram8-bit COREALUADDRESS AND DATA BUSOSC1VPPCONTROLPROGRAM(32 or 60 Kbyte

Electrical characteristics ST72321xx-Auto190/243 Doc ID 13829 Rev 119.3.4 External voltage detector (EVD) thresholdsSubject to general operating cond

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 191/24319.4 Supply current characteristicsThe following current consumption specified for

Electrical characteristics ST72321xx-Auto192/243 Doc ID 13829 Rev 1Power consumption vs fCPU: Flash devicesFigure 74. Typical IDD in Run modeFigure 75

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 193/243Figure 77. Typical IDD in Slow Wait mode19.4.2 Supply and clock managersThe previo

Electrical characteristics ST72321xx-Auto194/243 Doc ID 13829 Rev 119.4.3 On-chip peripheralsMeasured on LQFP64 generic board TA = 25°C, fCPU=4MHz.

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 195/24319.5 Clock and timing characteristicsSubject to general operating conditions for V

Electrical characteristics ST72321xx-Auto196/243 Doc ID 13829 Rev 119.5.3 Crystal and ceramic resonator oscillatorsThe ST7 internal clock can be supp

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 197/243 19.5.4 RC oscillators Figure 80. Typical fOSC(RCINT) ver

Electrical characteristics ST72321xx-Auto198/243 Doc ID 13829 Rev 119.5.5 PLL characteristics The user must take the PLL jitter into account

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 199/24319.6 Memory characteristics19.6.1 RAM and hardware registers 19.6.2 Flash

Contents ST72321xx-Auto2/243 Doc ID 13829 Rev 1Contents1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package pinout and pin description ST72321xx-Auto20/243 Doc ID 13829 Rev 12 Package pinout and pin description2.1 Package pinoutFigure 2. 64-pin LQFP

Electrical characteristics ST72321xx-Auto200/243 Doc ID 13829 Rev 119.7 EMC (electromagnetic compatibility) characteristicsSusceptibilitytests are pe

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 201/243 .19.7.2 EMI (electromagnetic interference)Based on a simple application r

Electrical characteristics ST72321xx-Auto202/243 Doc ID 13829 Rev 119.7.3 Absolute maximum ratings (electrical sensitivity)Based on two different tes

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 203/24319.8 I/O port pin characteristics19.8.1 General characteristicsSubject to general

Electrical characteristics ST72321xx-Auto204/243 Doc ID 13829 Rev 1 19.8.2 Output driving currentSubject to general operating conditions for

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 205/243 Figure 84. Typical VOL at VDD= 5V (standard) Figure 85. Typical V

Electrical characteristics ST72321xx-Auto206/243 Doc ID 13829 Rev 1Figure 87. Typical VOL versus VDD (standard)Figure 88. Typical VOL versus VDD (high

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 207/24319.9 Control pin characteristics19.9.1 Asynchronous RESET pinSubject to general op

Electrical characteristics ST72321xx-Auto208/243 Doc ID 13829 Rev 1Figure 90. RESET pin protection when LVD is enabledNote: 1 The reset network protec

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 209/243Figure 91. RESET pin protection when LVD is disabledNote: The reset network protect

ST72321xx-Auto Package pinout and pin descriptionDoc ID 13829 Rev 1 21/243Figure 3. 44-pin LQFP package pinoutMCO / AIN8 / PF0BEEP / (HS) PF1(HS) PF2O

Electrical characteristics ST72321xx-Auto210/243 Doc ID 13829 Rev 1Figure 92. Two typical applications with ICCSEL/VPP pin(1)1. When ICC mode is not r

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 211/24319.11 Communication interface characteristics19.11.1 SPI (serial peripheral interf

Electrical characteristics ST72321xx-Auto212/243 Doc ID 13829 Rev 1Figure 93. SPI slave timing diagram with CPHA = 0(1)1. Measurement points are done

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 213/243Figure 95. SPI master timing diagram(1)1. Measurement points are done at CMOS level

Electrical characteristics ST72321xx-Auto214/243 Doc ID 13829 Rev 119.11.2 I2C - inter IC control interfaceSubject to general operating conditions for

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 215/243Figure 96.Typical application with I2C BUS and timing diagram(1)1.Measurement point

Electrical characteristics ST72321xx-Auto216/243 Doc ID 13829 Rev 119.12 10-bit ADC characteristicsSubject to general operating conditions for VDD, f

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 217/243 Figure 99. Typical A/D converter application19.12.1 Analog power supply a

Electrical characteristics ST72321xx-Auto218/243 Doc ID 13829 Rev 119.12.2 General PCB design guidelinesTo obtain best results, some general design an

ST72321xx-Auto Electrical characteristicsDoc ID 13829 Rev 1 219/24319.12.3 ADC accuracyConditions: VDD=5V(1) Figure 101. ADC error classificat

Package pinout and pin description ST72321xx-Auto22/243 Doc ID 13829 Rev 12.2 Pin descriptionIn the device pin description table, the RESET configurat

Package characteristics ST72321xx-Auto220/243 Doc ID 13829 Rev 120 Package characteristicsFigure 102. 64-pin (14x14) low profile quad flat package out

ST72321xx-Auto Package characteristicsDoc ID 13829 Rev 1 221/243Figure 103. 64-pin (10x10) low profile quad flat package outline Table 138. 64

Package characteristics ST72321xx-Auto222/243 Doc ID 13829 Rev 120.1 Thermal characteristics 20.2 Ecopack informationIn order to meet environm

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 223/24321 Device configuration and ordering informationEach device is

Device configuration and ordering information ST72321xx-Auto224/243 Doc ID 13829 Rev 1 Table 141. Option byte 0 bit descriptionBit Name Functi

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 225/243 Note: On the chip, each I/O port has up to eig

Device configuration and ordering information ST72321xx-Auto226/243 Doc ID 13829 Rev 121.1.2 Flash ordering informationThe following Figure 105 serves

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 227/24321.2 ROM device ordering information and transfer of customer c

Device configuration and ordering information ST72321xx-Auto228/243 Doc ID 13829 Rev 1Figure 106. ST72P321xxx-Auto FastROM commercial product structur

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 229/243 Figure 107. ST72321xxx-Auto ROM commercial product stru

ST72321xx-Auto Package pinout and pin descriptionDoc ID 13829 Rev 1 23/24325 15 PF0/MCO/AIN8 I/O CTX ei1 X X X Port F0Main clock out (fOSC/2)ADC Analo

Device configuration and ordering information ST72321xx-Auto230/243 Doc ID 13829 Rev 1 ST72321-Auto Microcontroller FASTROM/ROM Option List(La

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 231/24321.3 Development tools21.3.1 IntroductionDevelopment tools for t

Device configuration and ordering information ST72321xx-Auto232/243 Doc ID 13829 Rev 1 21.3.5 Socket and emulator adapter informati

ST72321xx-Auto Device configuration and ordering informationDoc ID 13829 Rev 1 233/24321.4 ST7 application notesAll relevant ST7 application notes ca

Known limitations ST72321xx-Auto234/243 Doc ID 13829 Rev 122 Known limitations22.1 All Flash and ROM devices22.1.1 External RC optionThe external RC

ST72321xx-Auto Known limitationsDoc ID 13829 Rev 1 235/243To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is

Known limitations ST72321xx-Auto236/243 Doc ID 13829 Rev 1; check the semaphore status if edge is detected CP A,#01 jrne OUTcall call_routine; call th

ST72321xx-Auto Known limitationsDoc ID 13829 Rev 1 237/243; check for falling edgecp A,#$02jrne OUTTNZ Yjrne OUTLD A,#$01LD sema,A; set the semaphore

Known limitations ST72321xx-Auto238/243 Doc ID 13829 Rev 122.1.6 Clearing active interrupts outside interrupt routineWhen an active interrupt request

ST72321xx-Auto Known limitationsDoc ID 13829 Rev 1 239/24322.1.7 SCI wrong break durationDescriptionA single break character is sent by setting and r

Package pinout and pin description ST72321xx-Auto24/243 Doc ID 13829 Rev 141 29 PC6/SCK/ICCCLK I/O CTX XXXPort C6SPI Serial ClockICC Clock OutputCauti

Known limitations ST72321xx-Auto240/243 Doc ID 13829 Rev 122.1.9 TIMD set simultaneously with OC interruptIf the 16-bit timer is disabled at the same

ST72321xx-Auto Known limitationsDoc ID 13829 Rev 1 241/243Consequently, the LVD function is not guaranteed in the current silicon revision. For comple

Revision history ST72321xx-Auto242/243 Doc ID 13829 Rev 123 Revision history Table 146. Document revision historyDate Revision Changes05-Aug-2

ST72321xx-AutoDoc ID 13829 Rev 1 243/243 Please Read Carefully:Information in this document is provided solely in connection with ST products

ST72321xx-Auto Package pinout and pin descriptionDoc ID 13829 Rev 1 25/243 Legend / Abbreviations for Tab le 3 :Type: I = inputO = outputS = s

Register and memory map ST72321xx-Auto26/243 Doc ID 13829 Rev 13 Register and memory mapAs shown in Figure 4, the MCU is capable of addressing 64 Kby

ST72321xx-Auto Register and memory mapDoc ID 13829 Rev 1 27/243000Ch000Dh000EhPort EPEDRPEDDRPEORPort E Data RegisterPort E Data Direction RegisterPor

Register and memory map ST72321xx-Auto28/243 Doc ID 13829 Rev 1Note: Legend: x = undefined, R/W = read/write0040h Reserved Area (1 byte)0041h0042h0043

ST72321xx-Auto Flash program memoryDoc ID 13829 Rev 1 29/2434 Flash program memory4.1 IntroductionThe ST7 dual voltage High Density Flash (HDFlash) i

ST72321xx-Auto ContentsDoc ID 13829 Rev 1 3/2436.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flash program memory ST72321xx-Auto30/243 Doc ID 13829 Rev 1Figure 5. Memory map and sector address4.3.1 Readout protectionReadout protection, when se

ST72321xx-Auto Flash program memoryDoc ID 13829 Rev 1 31/243Figure 6. Typical ICC interface1. If the ICCCLK or ICCDATA pins are only used as outputs i

Flash program memory ST72321xx-Auto32/243 Doc ID 13829 Rev 14.6 IAP (in-application programming)This mode uses a BootLoader program previously stored

ST72321xx-Auto Central processing unit (CPU)Doc ID 13829 Rev 1 33/2435 Central processing unit (CPU)5.1 IntroductionThis CPU has a full 8-bit archite

Central processing unit (CPU) ST72321xx-Auto34/243 Doc ID 13829 Rev 15.3.1 Accumulator (A)The accumulator is an 8-bit general purpose register used to

ST72321xx-Auto Central processing unit (CPU)Doc ID 13829 Rev 1 35/243 These two bits are set/cleared by hardware when entering in int

Central processing unit (CPU) ST72321xx-Auto36/243 Doc ID 13829 Rev 1The stack pointer is a 16-bit register which is always pointing to the next free

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 37/2436 Supply, reset and clock management6.1 IntroductionThe device includes a r

Supply, reset and clock management ST72321xx-Auto38/243 Doc ID 13829 Rev 16.3 Phase locked loopIf the clock frequency input to the PLL is in the rang

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 39/243Crystal/ceramic oscillatorsThis family of oscillators has the advantage of p

Contents ST72321xx-Auto4/243 Doc ID 13829 Rev 19.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply, reset and clock management ST72321xx-Auto40/243 Doc ID 13829 Rev 16.5 Reset sequence manager (RSM)6.5.1 IntroductionThe reset sequence manage

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 41/243Figure 12. RESET sequence phases6.5.2 Asynchronous external RESET pinThe RE

Supply, reset and clock management ST72321xx-Auto42/243 Doc ID 13829 Rev 16.5.5 Internal watchdog RESETThe RESET sequence generated by an internal Wat

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 43/2436.6 System integrity management (SI)The System Integrity Management block c

Supply, reset and clock management ST72321xx-Auto44/243 Doc ID 13829 Rev 1Figure 14. Low voltage detector versus reset 6.6.2 Auxiliary voltage detecto

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 45/243Figure 15. Using the AVD to monitor VDD (AVDS bit = 0)Monitoring a voltage o

Supply, reset and clock management ST72321xx-Auto46/243 Doc ID 13829 Rev 1Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)6

ST72321xx-Auto Supply, reset and clock managementDoc ID 13829 Rev 1 47/2436.6.5 System Integrity (SI) Control/Status register (SICSR)

Supply, reset and clock management ST72321xx-Auto48/243 Doc ID 13829 Rev 1Application notesThe LVDRF flag is not cleared when another RESET type occur

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 49/2437 Interrupts7.1 IntroductionThe ST7 enhanced interrupt management provides the following features:●

ST72321xx-Auto ContentsDoc ID 13829 Rev 1 5/24312.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupts ST72321xx-Auto50/243 Doc ID 13829 Rev 1 Figure 17. Interrupt processing flowchart Servicing pending interrupts As several interrupt

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 51/243When an interrupt request is not serviced immediately, it is latched and then processed when its sof

Interrupts ST72321xx-Auto52/243 Doc ID 13829 Rev 1flag is set in the peripheral status registers and if the corresponding enable bit is set in the per

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 53/243Figure 20. Nested interrupt management7.5 Interrupt register description7.5.1 CPU CC register inter

Interrupts ST72321xx-Auto54/243 Doc ID 13829 Rev 1 7.5.2 Interrupt software priority registers (ISPRx)These four registers are read/write, wit

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 55/243The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bi

Interrupts ST72321xx-Auto56/243 Doc ID 13829 Rev 1 Table 20. Interrupt mappingNo.Source blockDescriptionRegister labelPriority order Exit from

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 57/2437.6 External interrupts7.6.1 I/O port interrupt sensitivityThe external interrupt sensitivity is con

Interrupts ST72321xx-Auto58/243 Doc ID 13829 Rev 1Figure 21. External interrupt control bitsIS10 IS11EICRSENSITIVITYCONTROLPBOR.3PBDDR.3IPB BITPB3ei2

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 59/2437.6.2 External interrupt control register (EICR) EICR Reset value: 0000 0000 (00h)7

Contents ST72321xx-Auto6/243 Doc ID 13829 Rev 113.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 11613.7

Interrupts ST72321xx-Auto60/243 Doc ID 13829 Rev 1 Table 22. Interrupt sensitivity - ei2 (port B3..0)IS11 IS10Exter

ST72321xx-Auto InterruptsDoc ID 13829 Rev 1 61/243 Table 26. Nested interrupts register map and reset valuesAddress (Hex.)Register label765432

Power saving modes ST72321xx-Auto62/243 Doc ID 13829 Rev 18 Power saving modes8.1 IntroductionTo give a large measure of flexibility to the applicatio

ST72321xx-Auto Power saving modesDoc ID 13829 Rev 1 63/243Figure 23. Slow mode clock transitions8.3 Wait modeWait mode places the MCU in a low power c

Power saving modes ST72321xx-Auto64/243 Doc ID 13829 Rev 1Figure 24. Wait mode flowchart1. Before servicing an interrupt, the CC register is pushed on

ST72321xx-Auto Power saving modesDoc ID 13829 Rev 1 65/2438.4 Active Halt and Halt modesActive Halt and Halt modes are the two lowest power consumpti

Power saving modes ST72321xx-Auto66/243 Doc ID 13829 Rev 1Figure 25. Active Halt timing overview1. This delay occurs only if the MCU exits Active Halt

ST72321xx-Auto Power saving modesDoc ID 13829 Rev 1 67/2438.4.2 Halt modeThe Halt mode is the lowest power consumption mode of the MCU. It is entered

Power saving modes ST72321xx-Auto68/243 Doc ID 13829 Rev 1Figure 28. Halt mode flowchart1. WDGHALT is an option bit. See Section 21.1.1: Flash configu

ST72321xx-Auto Power saving modesDoc ID 13829 Rev 1 69/243Halt mode recommendations● Make sure that an external event is available to wake up the micr

ST72321xx-Auto ContentsDoc ID 13829 Rev 1 7/24315 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 13515.1 Intro

I/O ports ST72321xx-Auto70/243 Doc ID 13829 Rev 19 I/O ports9.1 IntroductionThe I/O ports offer different functional modes:● transfer of data through

ST72321xx-Auto I/O portsDoc ID 13829 Rev 1 71/243Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout descriptio

I/O ports ST72321xx-Auto72/243 Doc ID 13829 Rev 1Figure 29. I/O port general block diagram Table 29. I/O port mode optionsConfiguration mode P

ST72321xx-Auto I/O portsDoc ID 13829 Rev 1 73/243 Table 30. I/O port configurationsHardware configurationInput(1)Open-drain output(2)Push-pull

I/O ports ST72321xx-Auto74/243 Doc ID 13829 Rev 1Caution: The alternate function must not be activated as long as the pin is configured as input with

ST72321xx-Auto I/O portsDoc ID 13829 Rev 1 75/2439.4 Low power modes 9.5 InterruptsThe external interrupt event generates an interrupt if the

I/O ports ST72321xx-Auto76/243 Doc ID 13829 Rev 1Related documentationSPI Communication between ST7 and EEPROM (AN 970)S/W implementation of I2C bus m

ST72321xx-Auto Watchdog timer (WDG)Doc ID 13829 Rev 1 77/24310 Watchdog timer (WDG)10.1 IntroductionThe Watchdog timer is used to detect the occurren

Watchdog timer (WDG) ST72321xx-Auto78/243 Doc ID 13829 Rev 1Figure 31. Watchdog block diagram10.4 How to program the watchdog timeoutFigure 32 shows

ST72321xx-Auto Watchdog timer (WDG)Doc ID 13829 Rev 1 79/243Figure 33. Exact timeout duration (tmin and tmax)WHERE:tmin0 = (LSB + 128) x 64 x tOSC2tma

Contents ST72321xx-Auto8/243 Doc ID 13829 Rev 116.7.2 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watchdog timer (WDG) ST72321xx-Auto80/243 Doc ID 13829 Rev 110.5 Low power modes 10.6 Hardware watchdog optionIf Hardware Watchdog is select

ST72321xx-Auto Watchdog timer (WDG)Doc ID 13829 Rev 1 81/24310.9 Register description10.9.1 Control register (WDGCR) WDGCR

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto82/243 Doc ID 13829 Rev 111 Main clock controller with real-time clock

ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)Doc ID 13829 Rev 1 83/243Figure 34.Main clock controller (MCC/RTC) block

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto84/243 Doc ID 13829 Rev 111.8 Main clock controller registers11.8.1 MCC

ST72321xx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)Doc ID 13829 Rev 1 85/243 11.8.2 MCC beep control register (MCC

Main clock controller with real-time clock and beeper (MCC/RTC) ST72321xx-Auto86/243 Doc ID 13829 Rev 1 Table 44. Main clock controller regis

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 87/24312 PWM auto-reload timer (ART)12.1 IntroductionThe Pulse Width Modulated Auto-Relo

PWM auto-reload timer (ART) ST72321xx-Auto88/243 Doc ID 13829 Rev 112.2 Functional description12.2.1 CounterThe free running 8-bit counter is fed by t

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 89/243Figure 36. Output compare control12.2.5 Independent PWM signal generationThis mode

ST72321xx-Auto ContentsDoc ID 13829 Rev 1 9/24319.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18519.1.

PWM auto-reload timer (ART) ST72321xx-Auto90/243 Doc ID 13829 Rev 1Figure 37. PWM auto-reload timer functionFigure 38. PWM signal from 0% to 100% duty

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 91/243Figure 39. External event detector example (3 counts)12.2.8 Input capture functionT

PWM auto-reload timer (ART) ST72321xx-Auto92/243 Doc ID 13829 Rev 112.2.9 External interrupt capabilityThis mode allows the input capture capabilities

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 93/24312.3 ART registers12.3.1 Control/status register (ARTCSR)

PWM auto-reload timer (ART) ST72321xx-Auto94/243 Doc ID 13829 Rev 112.3.2 Counter access register (ARTCAR) 12.3.3 Auto-reload regis

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 95/243 12.3.4 PWM control register (PWMCR) Table 49. P

PWM auto-reload timer (ART) ST72321xx-Auto96/243 Doc ID 13829 Rev 112.3.5 Duty cycle registers (PWMDCRx) A PWMDCRx register is assoc

ST72321xx-Auto PWM auto-reload timer (ART)Doc ID 13829 Rev 1 97/24312.3.7 Input capture registers (ARTICRx) ARTICRx Reset v

16-bit timer ST72321xx-Auto98/243 Doc ID 13829 Rev 113 16-bit timer13.1 IntroductionThe timer consists of a 16-bit free-running counter driven by a pr

ST72321xx-Auto 16-bit timerDoc ID 13829 Rev 1 99/24313.3 Functional description13.3.1 CounterThe main block of the Programmable Timer is a 16-bit free